Dr.-Ing. Mohammed Ali 

For modern wireless systems such as high-resolution imaging and high data-rate communications, wide bandwidth becomes crucial. This increases the need for broadband Front-Ends at frequencies beyond 100GHz and imposes challenges to the design of the frequency generation circuitry. Generating LO signals can be carried out by means of VCO’s. The high frequency VCOs suffer from several problems such as limited tunning range and high phase noise due to the low variable capacitors’ Q-factor beyond 100GHz. Alternatively, LO signals can be generated at lower frequencies (i.e. K- and/or Ka-Band) followed by long frequency multiplication chain. The former solution guarantees both reasonable phase noise and bandwidth. The main challenges of frequency multiplier design is the harmonic rejection and the silicon area. Several high order frequency multiplier designs have been carried out by cascading X2 and/or X3 multipliers. However, these designs consume large chip area and DC power. Alternatively, higher order frequency multiplication can be carried out using current reuse cascode structures. A promising solution that can be power and size efficient. However, other solutions can be investigated and implemented.