Mixed-Signal IC Design

  • Typ: Vorlesung (V)
  • Lehrstuhl: KIT-Fakultäten - KIT-Fakultät für Elektrotechnik und Informationstechnik
  • Semester: SS 2022
  • Ort:

    50.31 Raum 012
    50.31 Bauingenieure, Kollegiengebäude III (EG)

  • Zeit:

    Mo 25.04.2022
    14:00 - 15:30, wöchentlich



  • Dozent: Dr. Michele Caselle
  • SWS: 2
  • ECTS: 3
  • LVNr.: 2308443

Description:

Applying new skills to a variety of design applications is becoming increasingly critical for engineers. This holds true for industries including wireless communications, digital audio, digital telephony, SoC design and front-end ASICs for particle physics involving mixed-signal processing, and analog/digital conversion.

Whenever a computer or other piece of digital logic interacts with the real world, some sort of analog-to-digital or digital-to-analog conversion is required. Often a complex system’s ultimate performance depends more on its mixed signal data converters and oscillators as opposed to other components. Stringent performance requirements have been placed on technology including phase locked loop jitter, circuit noise, and sample-and-hold “droop.”

This course covers the fundamentals of data converters, Nyquist-rate converters, discrete-time signal processing, the central concept of oversampling and noise-shaping, and delta-sigma modulators. It is intended for engineers working with digital and analog signals, seeking to learn more about mixed-signal (analog plus digital) circuit design, analysis, and application.

Whether you are a "pure" digital or analog engineer, the material covered in this course will provide you with the skills necessary to excel in your field.

The course complements the already established courses in analog design (M-ETIT-100466) and digital design (M-ETIT-100473) diving into the design of mixed-signal integrated circuits.

Finally, they know various bonding techniques and printed circuit board design practices in order to connect the final ASIC to other chips and measurement equipment

Contents:

Sample-and-hold and track-and-hold circuits

Design an A/D or D/A converters

Development of time-to-digital converters and applications

Design phase lock loop (PLL) and DLL (Delay lock loop) circuits, including design details and benefits and disadvantages of each type

Digital data processing

Time interleaving, oversampling, decimation filters

Analog and digital advanced integrated circuit

 

Sommersemester: 2 SWS

Leistungspunkte: 3

Sprache: Englisch

Erfolgskontrolle(n): The success criteria will be determined by an oral examination (approx. 20-30 min.)

Modulnote: The module grade is the grade of the oral examination.

Voraussetzungen: None